In a liquid crystal display, in order to avoid a screen from flicking due to insufficient charging of a pixel electrode in a pixel structure, it is typically necessary to maintain a stable potential across a source and a drain of a transistor connected with the pixel electrode to thereby lower the difference in voltage between the source and the drain so as to reduce leakage current in the transistor.
Typically the transistor connected with the pixel electrode is in a single-gate structure, where when a gate scan signal is stopped from being loaded to a gate line, a node between a storage capacitor and the transistor is floating, and also due to a parasitic capacitance between the gate line and a data line, the potential of the node may so fluctuate with elapsing time that the potential may gradually deviate from the potential of a data signal loaded to the data line, thus resulting in a larger difference in voltage between the source and the drain of the transistor, which may come with higher leakage current, thus degrading the display quality of a picture. In the prior art, in order to reduce the leakage current of the transistor, typically the single-gate transistor is replaced with a dual-gate transistor. FIG. 1A illustrates a top view of an array substrate, where 101 represents a gate line, 102 represents a data line, 103 represents a common electrode, and 104 represents a pixel electrode; and FIG. 1B illustrates an equivalent circuit diagram corresponding to FIG. 1A, where there are a dual-gate structure including a first transistor T1 and a second transistor T2, and a storage capacitor C0; the storage capacitor C0 has a terminal m, which is the pixel electrode 104, and a terminal n, which is the common electrode 103. Both the gate of the first transistor T1, and the gate of the second transistor T2 are connected with the gate line GATE, the drain of the first transistor T1 is connected with the pixel electrode 104, and the source of the second transistor T2 is connected with the data line DATA; and when an active gate scan signal is loaded to the gate line GATE, both the first transistor T1 and the second transistor T2 are turned on, and a data signal input on the data line DATA flows through the first transistor T1 and the second transistor T2 to charge the pixel electrode 104 connected with the node P0. However if the active gate scan signal is stopped from being loaded to the gate line GATE, both the first transistor T1 and the second transistor T2 are turned off, and both the node P0 and the node P1 are floating; and also due to a parasitic capacitor between the gate line GATE and the data line DATA, the potentials of the node P0 and the node P1 fluctuate as the first transistor T1 and the second transistor T2 are turned off, and the time is elapsing, where particularly the potential of the node P1 more significantly fluctuate. As the result of some simulation showed, the potential of the node P1 may fluctuate by approximately 11V at most, thus resulting in a larger difference in voltage between the source and the drain of the first transistor T1, which may come with larger leakage current. Apparently the leakage current may not be significantly reduced in the transistor with dual gates.
In view of this, it is highly desirable for those skilled in the art to greatly reduce the leakage current in the transistor to thereby charge the pixel electrode sufficiently so as to improve the quality of a picture on the liquid crystal display.